Copyright(C) 1994,1995,1996,1997 Terumasa KODAKA , Takeshi KONO
■Supercore590 Wildcat chipset
Applicable models: PC-9821Xa16, Xa13, Xa12, Xa10, Xa9, Xa7, Xa7e, Xt16, Xt13, Xv13, Xb10, V10, V7
Explanation: o PC-9821Xa10, Xa9, Xa7, Xt13, Xa12, Xa7e use the Wildcat chipset
from VLSI Technologies as the PCI chipset. The Wildcat chipset controls the
PCI bus, memory, and cache.
o The CPU can configure various settings for the Wildcat chipset through the
PCI configuration register.
Related INT 1Ah - Function B1h
INT 1Fh - Function CCh
F8E8:0004h bit 5
■PCMC(PCI,Cache & Memory Controller)
Vendor ID 1004h(Intel)
Device ID 0007h
Base class 06h(Bridge device)
Subclass 00h(PCI-HOST CPU bridge)
-------------------------------------------------------------------------------
PCI 00h,01h
Name Vendor ID(VID)
Undocumented
Function
[READ]
bit 15-0: Vendor ID(VID)
* VLSI's vendor ID is 1004h.
Explanation o Returns the PCMC vendor ID. This register is read-only.
PCI 02h,03h
Name Device ID (DID)
Undocumented
Function
[READ]
bit 15-0: Device ID (DID)
* The device ID for VLSI's PCMC (82434LX/NX) is 04A3h.
Explanation o Returns the Wildcat device ID. This register is read-only.
PCI 04h,05h
Name Command Register (PCICMD)
Undocumented
Function
[READ/WRITE]
bit 15-9: Reserved
bit 8: SERR# Enable (SERRE)
1 = Enabled
0 = Disenabled
bit 7: Reserved
bit 6: Parity Error Enable (PERRE)
1 = Support parity checking on PCI
0 = No Parity checking on PCI
bit 5-3: Reserved
bit 2: Bus Master Enable (BME)
1 = Enabled
0 = Disenabled
* This bit is read-only.
Always Enabled.
bit 1: Memory Access Enable (MAE)
1 = Enabled
0 = Disenabled
bit 0: I/O Access Enable (IOAE)
1 = Enabled
0 = Disenabled
* This bit is read-only.
Always Disenabled.
Description o Sets the basic capabilities of PCMC.
PCI 06h,07h
Name Status Register (PCISTS)
Undocumented
Function
[READ/WRITE]
bit 15: Reserved
bit 14: System Error Transmission (SSE)
1 = SERR# asserted by PCMC
0 = SERR# not asserted by PCMC
bit 13: Master Abort Receive Status (RMAS)
1 = Master abort
0 = No master abort
bit 12: Target Abort Receive Status (RTAS)
1 = Target abort
0 = No target abort
bit 11: Reserved
bit 10,9: DEVSEL# Timing (DEVT)
* This bit is read-only. Always 10b.
bit 8: Data Parity Detect (DPD)
1 = PCI Data Parity Error Detected
0 = No PCI Data Parity Error Detected
bit 7-0: Reserved
Explanation o Reads the status of PCI bus errors, etc.
PCI 08h
Name Revision ID (RID)
Undocumented
Function
[READ]
Bits 7-0: Revision ID (RID)
* Returns the revision ID of the PCMC.
Description o Returns the revision ID of the 82434 (PCMC). This register is read-only.
PCI 09h
Name Register Level Programming Interface (RLPI)
Undocumented
Function
[READ]
Bits 7-0: Register Level Programming Interface (RLPI)
* PCMC returns 00h.
Description o Indicates that the PCMC does not have a register level programming interface.
This register is read-only.
PCI 0Ah
Name Subclass Code (SCCD)
Undocumented
Function
[READ]
Bits 7-0: Subclass Code (SCCD)
* PCMC returns 00h.
Description o Indicates that the PCMC is a bridge device between the host CPU and the PCI bus.
This register is read-only.
PCI 0Bh
Name Base Class Code (BCCD)
Undocumented
Function
[READ]
bit 7-0: Base Class Code (BCCD)
* Initial value 06h
Explanation o Indicates that the PCMC is a bridge device.
This register is read-only.
PCI 0Dh
Name Master Latency Timer (MLT)
Undocumented
Function
[READ/WRITE]
Bit 7-4: Master Latency Timer Count Value
Bit 3-0: Reserved
Explanation o Sets the PCI bus occupation time for PCMC.
PCI 0Fh
Name BIST Register (BIST)
Undocumented
Function
[READ]
Bit 7: BIST Support
Bit 6: BIST Start
Bit 5,4: Reserved
Bit 3-0: Completion Code
Explanation o Supercord590 does not support BIST (Bulid In Self Test), so 00h is always read.
PCI 54h
Name Unknown
Undocumented
Function
[READ/WRITE]
bit 7,6: CPU internal cache
11b = Unknown
10b = CPU cache disabled
01b = CPU cache enabled
00b = 2nd cache enabled
bit 5-1: Unknown
bit 0: Unknown
Explanation o Controls cache
Related I/O 043Fh - A0h
PCI 55h
Name Unknown
Undocumented
Function
[READ/WRITE]
bit 7: Unknown
bit 6: CPU cache
1 = Enabled
0 = Disabled
bit 5,4: Unknown
bit 3: Cache miss
1 = Cache miss
0 = Cache hit
* Cleared by writing 1
bit 2-0: Unknown
Explanation o Controls cache
Related I/O 043Fh - A0h